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Searched refs:OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h15839 #define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK … macro
H A Ddcn_3_0_1_sh_mask.h24547 #define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK … macro
H A Ddcn_3_2_1_sh_mask.h25918 #define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK … macro
H A Ddcn_3_1_2_sh_mask.h30852 #define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK … macro
H A Ddcn_3_1_5_sh_mask.h28819 #define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK … macro
H A Ddcn_3_1_6_sh_mask.h31618 #define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK … macro
H A Ddcn_3_0_2_sh_mask.h27895 #define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK … macro
H A Ddcn_3_1_4_sh_mask.h32761 #define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK … macro
H A Ddcn_3_0_0_sh_mask.h31425 #define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK … macro
H A Ddcn_3_2_0_sh_mask.h25915 #define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK … macro