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Searched refs:OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h15196 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_3_0_3_sh_mask.h15344 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_3_0_1_sh_mask.h24052 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_2_1_0_sh_mask.h28494 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_3_2_1_sh_mask.h25446 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_1_0_sh_mask.h22603 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_3_1_2_sh_mask.h30367 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_3_1_5_sh_mask.h28363 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_3_1_6_sh_mask.h31133 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_3_0_2_sh_mask.h27400 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_3_1_4_sh_mask.h32289 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_3_0_0_sh_mask.h30930 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_2_0_0_sh_mask.h31841 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro
H A Ddcn_3_2_0_sh_mask.h25443 #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK … macro