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Searched refs:OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h15190 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h15338 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h24046 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h28488 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h25440 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_1_0_sh_mask.h22597 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h30361 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h28357 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h31127 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h27394 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h32283 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h30924 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h31835 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h25437 #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT … macro