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Searched refs:OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h14340 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h14449 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h23157 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h27571 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h24574 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_1_0_sh_mask.h21705 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h29484 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h27509 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h30250 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h26505 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h31417 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h30036 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h30921 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h24571 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT … macro