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Searched refs:OR_SCY_5_CLK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/include/
H A Dmpc8xx.h241 #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ macro
/openbmc/linux/arch/powerpc/include/asm/
H A D8xx_immap.h132 #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ macro