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Searched refs:OPC_RISC_SW (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dinstmap.h144 OPC_RISC_SW = OPC_RISC_STORE | (0x2 << 12), enumerator
H A Dcpu_helper.c1640 xinsn = OPC_RISC_SW; in riscv_transformed_insn()
1708 xinsn = OPC_RISC_SW; in riscv_transformed_insn()