Searched refs:OPC_JALR (Results 1 – 7 of 7) sorted by relevance
/openbmc/linux/arch/riscv/include/asm/ |
H A D | module.h | 60 #define OPC_JALR 0x0067 macro 86 OPC_JALR | (REG_T1 << 15) in emit_plt_entry()
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/openbmc/qemu/tcg/riscv/ |
H A D | tcg-target.c.inc | 168 OPC_JALR = 0x67, 1595 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); 1603 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); 1936 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1968 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); 2817 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 2831 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
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/openbmc/qemu/target/mips/tcg/ |
H A D | micromips_translate.c.inc | 805 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 4); 810 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 2); 932 gen_compute_branch(ctx, OPC_JALR, 2, (ctx->opcode >> 5) & 0x1f, 1193 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0); 1196 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 4); 1203 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2);
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H A D | mips16e_translate.c.inc | 942 op = OPC_JALR;
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H A D | nanomips_translate.c.inc | 1144 case OPC_JALR: 1183 case OPC_JALR: 4350 gen_compute_branch_nm(ctx, OPC_JALR, 4, rs, rt, 0); 4750 gen_compute_branch_nm(ctx, OPC_JALR, 2,
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H A D | translate.c | 228 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */ enumerator 4436 case OPC_JALR: in gen_compute_branch() 4510 case OPC_JALR: in gen_compute_branch() 13275 case OPC_JALR: in decode_opc_special()
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/openbmc/qemu/tcg/mips/ |
H A D | tcg-target.c.inc | 262 OPC_JALR = OPC_SPECIAL | 011, 344 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 734 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 1116 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
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