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Searched refs:ODR (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_gpio-test.c33 #define ODR 0x14 macro
190 gpio_writel(GPIO_A, ODR, 0xDEADBEEF); in test_idr_reset_value()
195 gpio_writel(GPIO_B, ODR, 0xDEADBEEF); in test_idr_reset_value()
200 gpio_writel(GPIO_C, ODR, 0xDEADBEEF); in test_idr_reset_value()
205 gpio_writel(GPIO_H, ODR, 0xDEADBEEF); in test_idr_reset_value()
212 uint32_t odr = gpio_readl(GPIO_A, ODR); in test_idr_reset_value()
219 g_assert_cmphex(odr, ==, reset(GPIO_A, ODR)); in test_idr_reset_value()
227 odr = gpio_readl(GPIO_B, ODR); in test_idr_reset_value()
234 g_assert_cmphex(odr, ==, reset(GPIO_B, ODR)); in test_idr_reset_value()
242 odr = gpio_readl(GPIO_C, ODR); in test_idr_reset_value()
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/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dimmap.c186 ODR, in do_iopset() enumerator
218 cmd = ODR; in do_iopset()
259 case ODR: in do_iopset()
/openbmc/libmctp/docs/bindings/
H A Dvendor-ibm-astlpc.md74 Output Data Register (ODR).
76 ### ODR: Output Data Register
78 One of the three register interfaces exposed by a KCS device. The ODR is a one
85 indication of IBF and OBF events on the input (IDR) and output (ODR) buffers.
135 (ODR) and the Input Data Register (IDR). The ODR is written by the BMC and read
139 to determine if there is data in the ODR or IDR. These are single-bit flags,
141 hardware when data has been written to the corresponding ODR/IDR buffer (and
153 interrupt to signal a status update by writing a dummy command to ODR after
329 | 1 | The BMC writes a command value to ODR |
332 | 4 | If OBF is set, the host reads the BMC command from ODR |
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/openbmc/docs/designs/
H A Dbmc-service-failure-debug-and-recovery.md358 As STR is polled by the host it's not necessary for the BMC to write to ODR. The