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Searched refs:NumDispClkLevelsEnabled (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c585 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn31_clk_mgr_helper_populate_bw_params()
586 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn31_clk_mgr_helper_populate_bw_params()
587 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()
588 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()
756 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn31_clk_mgr_construct()
767 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn31_clk_mgr_construct()
H A Ddcn31_smu.h141 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c589 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn314_clk_mgr_helper_populate_bw_params()
590 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn314_clk_mgr_helper_populate_bw_params()
591 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()
592 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()
798 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn314_clk_mgr_construct()
809 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn314_clk_mgr_construct()
H A Ddcn314_smu.h60 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h120 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
H A Dsmu13_driver_if_yellow_carp.h132 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
H A Dsmu11_driver_if_vangogh.h145 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member
H A Dsmu13_driver_if_v13_0_4.h133 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c508 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn316_clk_mgr_helper_populate_bw_params()
509 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn316_clk_mgr_helper_populate_bw_params()
510 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()
511 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()
H A Ddcn316_smu.h87 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h79 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
H A Ddcn315_clk_mgr.c532 …table.entries[i-1].dispclk_mhz = clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1]; in dcn315_clk_mgr_helper_populate_bw_params()
533 …k_table.entries[i-1].dppclk_mhz = clock_table->DppClocks[clock_table->NumDispClkLevelsEnabled - 1]; in dcn315_clk_mgr_helper_populate_bw_params()
683 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn315_clk_mgr_construct()
694 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn315_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h116 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member