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Searched refs:NVBL_PLLP_KHZ (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.h13 #define NVBL_PLLP_KHZ 216000 macro
17 #define NVBL_PLLP_KHZ 408000 macro
H A Dcpu.c392 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ); in clock_enable_coresight()
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dcpu.c158 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); in t114_init_clocks()
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dcpu.c203 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); in tegra124_init_clocks()