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Searched refs:NUM_OF_CACHELINE (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mt7620/
H A Dddr_calibrate.c25 #define NUM_OF_CACHELINE 128 macro
91 nc_addr < (0xa0000000 + DRAM_BUTTOM - NUM_OF_CACHELINE * 32); in test_loop()
97 cal_memset(((u8 *)c_addr), 0x1F, NUM_OF_CACHELINE * 32); in test_loop()
98 cal_patgen(nc_addr, NUM_OF_CACHELINE * 8, pat); in test_loop()
114 NUM_OF_CACHELINE * 32); in test_loop()
117 for (i = 0; i < NUM_OF_CACHELINE * 8; i++) { in test_loop()
122 for (i = 0; i < NUM_OF_CACHELINE * 8; i++) { in test_loop()