Searched refs:MinVddcPhases (Results 1 – 6 of 6) sorted by relevance
107 uint32_t MinVddcPhases; member138 uint32_t MinVddcPhases; member171 uint32_t MinVddcPhases; member245 uint8_t MinVddcPhases; member
2626 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()2868 memory_level->MinVddcPhases = 1; in ci_populate_single_memory_level()2874 &memory_level->MinVddcPhases); in ci_populate_single_memory_level()2931 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); in ci_populate_single_memory_level()2999 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); in ci_populate_smc_acpi_level()3011 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()3197 graphic_level->MinVddcPhases = 1; in ci_populate_single_graphic_level()3203 &graphic_level->MinVddcPhases); in ci_populate_single_graphic_level()3224 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); in ci_populate_single_graphic_level()3313 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()[all …]
50 uint32_t MinVddcPhases; member80 uint32_t MinVddcPhases; member113 uint32_t MinVddcPhases; member191 uint8_t MinVddcPhases; member
909 graphic_level->MinVddcPhases = 1; in iceland_populate_single_graphic_level()915 &graphic_level->MinVddcPhases); in iceland_populate_single_graphic_level()945 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases); in iceland_populate_single_graphic_level()1258 memory_level->MinVddcPhases = 1; in iceland_populate_single_memory_level()1262 memory_clock, &memory_level->MinVddcPhases); in iceland_populate_single_memory_level()1325 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases); in iceland_populate_single_memory_level()1445 table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1; in iceland_populate_smc_acpi_level()1493 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in iceland_populate_smc_acpi_level()
427 level->MinVddcPhases = 1; in ci_populate_single_graphic_level()433 &level->MinVddcPhases); in ci_populate_single_graphic_level()458 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVddcPhases); in ci_populate_single_graphic_level()1212 memory_level->MinVddcPhases = 1; in ci_populate_single_memory_level()1216 memory_clock, &memory_level->MinVddcPhases); in ci_populate_single_memory_level()1279 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases); in ci_populate_single_memory_level()1399 table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()1447 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()1536 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()