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Searched refs:Mask (Results 1 – 25 of 89) sorted by relevance

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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.core_prefetch7 Here 0x02 can be replaced with any valid value except Mask[0] bit. It
8 represents 64 bit mask. The 64-bit Mask has one bit for each core.
9 Mask[0] = core0
10 Mask[1] = core1
11 Mask[2] = core2
16 core0 prefetch should not be disabled i.e. Mask[0] should never be set.
17 Setting Mask[0] may lead to undefined behavior.
/openbmc/linux/drivers/staging/rtl8192e/
H A Drtl819x_Qos.h110 u8 Mask; member
116 u8 Mask; member
125 u8 Mask; member
139 u8 Mask; member
151 u8 Mask; member
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dti-abb-regulator.txt25 - ti,tranxdone-status-mask: Mask to the int-register to write-to-clear mask
36 RBB enable efuse Mask: (See Optional properties)
37 FBB enable efuse Mask: (See Optional properties)
38 Vset value efuse Mask: (See Optional properties)
58 RBB enable efuse Mask: Optional if 'efuse-address' register is defined.
61 FBB enable efuse Mask: Optional if 'efuse-address' register is defined.
65 Vset value efuse Mask: Mandatory if ldo-address is set. Picks up from
/openbmc/u-boot/doc/
H A DREADME.mpc83xx.ddrecc37 1. Set 1 bit in Data Path Error Inject Mask
49 Memory Data Path Error Injection Mask High/Low: 00000001 00000000
81 1. Set more than 1 bit in Data Path Error Inject Mask
94 Memory Data Path Error Injection Mask High/Low: 00000001 00000001
122 1. Set 1 bit in Data Path Error Inject Mask
H A DREADME.m54418twr96 CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
134 CPU: Freescale MCF54418 (Mask:a3 Version:1)
/openbmc/linux/drivers/video/fbdev/via/
H A Dvt1636.c60 data = (data & (~io_data.Mask)) | io_data.Data; in viafb_gpio_i2c_write_mask_lvds()
163 io_data.Mask = 0x1F; in set_dpa_vt1636()
169 io_data.Mask = 0x0F; in set_dpa_vt1636()
/openbmc/linux/Documentation/scsi/
H A Dhptiop.rst29 0x28 Inbound Interrupt Mask Register
31 0x34 Outbound Interrupt Mask Register
47 0x28 Inbound Interrupt Mask Register
49 0x34 Outbound Interrupt Mask Register
60 0x20404 Inbound Interrupt Mask Register
62 0x2040C Outbound Interrupt Mask Register
/openbmc/linux/Documentation/sound/designs/
H A Dcontrol-names.rst135 IEC958 [...] [Playback|Capture] Mask consumer and professional mask
136 IEC958 [...] [Playback|Capture] Con Mask consumer mask
137 IEC958 [...] [Playback|Capture] Pro Mask professional mask
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-queues6 Mask of the CPU(s) currently enabled to participate into the
40 Mask of the CPU(s) currently enabled to participate into the
50 Mask of the receive queue(s) currently enabled to participate
H A Dsysfs-driver-pciback9 Device.Function-Register:Size:Mask (Domain is optional).
/openbmc/linux/Documentation/sound/cards/
H A Dimg-spdif-in.rst8 * name='IEC958 Capture Mask',index=0
16 is being received. The 'IEC958 Capture Mask' shows which bits can be read
/openbmc/linux/arch/arm/mm/
H A Dabort-macro.S18 and \tmp, \tmp, # 0xfe00 @ Mask opcode field
H A Dproc-v7m.S252 .long 0x000f0000 @ Mask for ID
/openbmc/openbmc-test-automation/ipmi/
H A Dtest_ipmi_network_configuration.robot49 Valid Value lan_print_output['Subnet Mask'] ["${NETMASK}"]
123 Valid Value lan_config['Subnet Mask'] ['${subnet_mask}']
167 Valid Value lan_config['Subnet Mask'] ['${subnet_mask}']
/openbmc/linux/Documentation/networking/devlink/
H A Ddevlink-selftests.rst9 Tests Mask
/openbmc/linux/fs/afs/
H A Dafs_vl.h107 __be32 Mask; member
/openbmc/qemu/docs/specs/
H A Divshmem-spec.rst64 0 4 read/write 0 Interrupt Mask
82 In revision 0 of the device, Interrupt Status and Mask Register
85 Mask is non-zero and the device has no MSI-X capability. Interrupt
120 masked by the Interrupt Mask register. The device is not capable to
H A Dvmw_pvscsi-spec.rst95 a. Mask interrupts
/openbmc/linux/Documentation/userspace-api/media/rc/
H A Dlirc-set-transmitter-mask.rst29 Mask with channels to enable tx. Channel 0 is the least significant bit.
/openbmc/linux/arch/alpha/lib/
H A Dev6-memset.S209 mskqh $7,$6,$2 # U : Mask final quad
387 mskqh $7,$6,$2 # U : Mask final quad
575 mskqh $7,$6,$2 # U : Mask final quad
/openbmc/u-boot/board/freescale/m53017evb/
H A DREADME107 CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
147 CPU: Freescale MCF53015 (Mask:76 Version:0)
/openbmc/u-boot/board/freescale/m52277evb/
H A DREADME98 CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
142 CPU: Freescale MCF52277 (Mask:6c Version:0)
/openbmc/linux/Documentation/networking/device_drivers/appletalk/
H A Dcops.rst53 inet addr:192.168.1.2 Bcast:192.168.1.255 Mask:255.255.255.0
/openbmc/u-boot/board/Synology/ds109/
H A Dopenocd.cfg67 mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
/openbmc/linux/Documentation/virt/kvm/arm/
H A Dhyp-abi.rst57 Mask all exceptions, disable the MMU, clear I+D bits, move the arguments

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