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Searched refs:MXC_CCM_CCSR_PLL4_SW_CLK_SEL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c687 writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL, in config_pll_clk()
693 writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL, in config_pll_clk()
/openbmc/u-boot/arch/arm/include/asm/arch-mx5/
H A Dcrm_regs.h88 #define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9) macro