Searched refs:MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (Results 1 – 2 of 2) sorted by relevance
82 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); in cm_fx6_enable_hdmi()113 clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); in cm_fx6_setup_display()
809 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) macro