Searched refs:MX6_IOM_DRAM_RESET (Results 1 – 20 of 20) sorted by relevance
| /openbmc/u-boot/arch/arm/include/asm/arch-mx6/ |
| H A D | mx6sl-ddr.h | 23 #define MX6_IOM_DRAM_RESET 0x020e0320 macro
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| H A D | mx6sx-ddr.h | 26 #define MX6_IOM_DRAM_RESET 0x020e0340 macro
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| H A D | mx6ul-ddr.h | 31 #define MX6_IOM_DRAM_RESET 0x020e0288 macro
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| H A D | mx6q-ddr.h | 23 #define MX6_IOM_DRAM_RESET 0x020e057c macro
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| H A D | mx6dl-ddr.h | 25 #define MX6_IOM_DRAM_RESET 0x020e0494 macro
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| /openbmc/u-boot/board/advantech/dms-ba16/ |
| H A D | ddr-setup.cfg | 9 DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
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| /openbmc/u-boot/board/aristainetos/ |
| H A D | ddr-setup2.cfg | 27 DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
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| H A D | ddr-setup.cfg | 27 DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
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| /openbmc/u-boot/board/boundary/nitrogen6x/ |
| H A D | ddr-setup.cfg | 60 DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
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| /openbmc/u-boot/board/toradex/apalis_imx6/ |
| H A D | ddr-setup.cfg | 61 DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
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| H A D | apalis_imx6.c | 945 MX6_IOM_DRAM_RESET, 0x00020030,
1064 MX6_IOM_DRAM_RESET, 0x00020030,
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| /openbmc/u-boot/board/toradex/colibri_imx6/ |
| H A D | ddr-setup.cfg | 61 DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
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| H A D | colibri_imx6.c | 797 MX6_IOM_DRAM_RESET, 0x00020030,
930 MX6_IOM_DRAM_RESET, 0x00020030,
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| /openbmc/u-boot/board/tqc/tqma6/ |
| H A D | tqma6dl.cfg | 40 DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
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| H A D | tqma6q.cfg | 40 DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
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| H A D | tqma6s.cfg | 40 DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
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| /openbmc/u-boot/board/logicpd/imx6/ |
| H A D | imx6logic.c | 267 MX6_IOM_DRAM_RESET, 0x00000030,
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| /openbmc/u-boot/board/ge/bx50v3/ |
| H A D | bx50v3.cfg | 30 DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
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| /openbmc/u-boot/board/seco/mx6quq7/ |
| H A D | mx6quq7-2g.cfg | 66 DATA 4, MX6_IOM_DRAM_RESET, 0x00000028
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| /openbmc/u-boot/board/barco/titanium/ |
| H A D | imximage.cfg | 66 DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
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