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Searched refs:MV_DDR3_TRAINING_ERR_PBS_ADLL_SHR_1PHASE (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.h232 #define MV_DDR3_TRAINING_ERR_PBS_ADLL_SHR_1PHASE 0xDD302010 macro
H A Dddr3_pbs.c220 return MV_DDR3_TRAINING_ERR_PBS_ADLL_SHR_1PHASE; in ddr3_pbs_tx()