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Searched refs:MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7834 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x00000004 macro
H A Ddce_8_0_sh_mask.h10354 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 macro
H A Ddce_10_0_sh_mask.h10052 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 macro
H A Ddce_11_0_sh_mask.h9746 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 macro
H A Ddce_11_2_sh_mask.h11024 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 macro