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Searched refs:MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7833 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x00000010L macro
H A Ddce_8_0_sh_mask.h10353 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 macro
H A Ddce_10_0_sh_mask.h10051 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 macro
H A Ddce_11_0_sh_mask.h9745 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 macro
H A Ddce_11_2_sh_mask.h11023 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 macro