1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* $Date: 2005/03/07 23:59:05 $ $RCSfile: mv88e1xxx.h,v $ $Revision: 1.13 $ */
3 #ifndef CHELSIO_MV8E1XXX_H
4 #define CHELSIO_MV8E1XXX_H
5 
6 #ifndef BMCR_SPEED1000
7 # define BMCR_SPEED1000 0x40
8 #endif
9 
10 #ifndef ADVERTISE_PAUSE
11 # define ADVERTISE_PAUSE 0x400
12 #endif
13 #ifndef ADVERTISE_PAUSE_ASYM
14 # define ADVERTISE_PAUSE_ASYM 0x800
15 #endif
16 
17 /* Gigabit MII registers */
18 #define MII_GBCR 9       /* 1000Base-T control register */
19 #define MII_GBSR 10      /* 1000Base-T status register */
20 
21 /* 1000Base-T control register fields */
22 #define GBCR_ADV_1000HALF         0x100
23 #define GBCR_ADV_1000FULL         0x200
24 #define GBCR_PREFER_MASTER        0x400
25 #define GBCR_MANUAL_AS_MASTER     0x800
26 #define GBCR_MANUAL_CONFIG_ENABLE 0x1000
27 
28 /* 1000Base-T status register fields */
29 #define GBSR_LP_1000HALF  0x400
30 #define GBSR_LP_1000FULL  0x800
31 #define GBSR_REMOTE_OK    0x1000
32 #define GBSR_LOCAL_OK     0x2000
33 #define GBSR_LOCAL_MASTER 0x4000
34 #define GBSR_MASTER_FAULT 0x8000
35 
36 /* Marvell PHY interrupt status bits. */
37 #define MV88E1XXX_INTR_JABBER          0x0001
38 #define MV88E1XXX_INTR_POLARITY_CHNG   0x0002
39 #define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010
40 #define MV88E1XXX_INTR_DOWNSHIFT       0x0020
41 #define MV88E1XXX_INTR_MDI_XOVER_CHNG  0x0040
42 #define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080
43 #define MV88E1XXX_INTR_FALSE_CARRIER   0x0100
44 #define MV88E1XXX_INTR_SYMBOL_ERROR    0x0200
45 #define MV88E1XXX_INTR_LINK_CHNG       0x0400
46 #define MV88E1XXX_INTR_AUTONEG_DONE    0x0800
47 #define MV88E1XXX_INTR_PAGE_RECV       0x1000
48 #define MV88E1XXX_INTR_DUPLEX_CHNG     0x2000
49 #define MV88E1XXX_INTR_SPEED_CHNG      0x4000
50 #define MV88E1XXX_INTR_AUTONEG_ERR     0x8000
51 
52 /* Marvell PHY specific registers. */
53 #define MV88E1XXX_SPECIFIC_CNTRL_REGISTER               16
54 #define MV88E1XXX_SPECIFIC_STATUS_REGISTER              17
55 #define MV88E1XXX_INTERRUPT_ENABLE_REGISTER             18
56 #define MV88E1XXX_INTERRUPT_STATUS_REGISTER             19
57 #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER       20
58 #define MV88E1XXX_RECV_ERR_CNTR_REGISTER                21
59 #define MV88E1XXX_RES_REGISTER                          22
60 #define MV88E1XXX_GLOBAL_STATUS_REGISTER                23
61 #define MV88E1XXX_LED_CONTROL_REGISTER                  24
62 #define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER          25
63 #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER     26
64 #define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER      27
65 #define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER         28
66 #define MV88E1XXX_EXTENDED_ADDR_REGISTER                29
67 #define MV88E1XXX_EXTENDED_REGISTER                     30
68 
69 /* PHY specific control register fields */
70 #define S_PSCR_MDI_XOVER_MODE    5
71 #define M_PSCR_MDI_XOVER_MODE    0x3
72 #define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
73 #define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE)
74 
75 /* Extended PHY specific control register fields */
76 #define S_DOWNSHIFT_ENABLE 8
77 #define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
78 
79 #define S_DOWNSHIFT_CNT    9
80 #define M_DOWNSHIFT_CNT    0x7
81 #define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
82 #define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT)
83 
84 /* PHY specific status register fields */
85 #define S_PSSR_JABBER 0
86 #define V_PSSR_JABBER (1 << S_PSSR_JABBER)
87 
88 #define S_PSSR_POLARITY 1
89 #define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
90 
91 #define S_PSSR_RX_PAUSE 2
92 #define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
93 
94 #define S_PSSR_TX_PAUSE 3
95 #define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
96 
97 #define S_PSSR_ENERGY_DETECT 4
98 #define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
99 
100 #define S_PSSR_DOWNSHIFT_STATUS 5
101 #define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
102 
103 #define S_PSSR_MDI 6
104 #define V_PSSR_MDI (1 << S_PSSR_MDI)
105 
106 #define S_PSSR_CABLE_LEN    7
107 #define M_PSSR_CABLE_LEN    0x7
108 #define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
109 #define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
110 
111 #define S_PSSR_LINK 10
112 #define V_PSSR_LINK (1 << S_PSSR_LINK)
113 
114 #define S_PSSR_STATUS_RESOLVED 11
115 #define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
116 
117 #define S_PSSR_PAGE_RECEIVED 12
118 #define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
119 
120 #define S_PSSR_DUPLEX 13
121 #define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
122 
123 #define S_PSSR_SPEED    14
124 #define M_PSSR_SPEED    0x3
125 #define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
126 #define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
127 
128 #endif
129