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Searched refs:MUX_M1 (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhikey960-pinctrl.dtsi30 0x008 MUX_M1 /* PMU1_SSI */
31 0x00c MUX_M1 /* PMU2_SSI */
32 0x010 MUX_M1 /* PMU_CLKOUT */
33 0x100 MUX_M1 /* PMU_HKADC_SSI */
51 0x058 MUX_M1 /* ISP_CLK0 */
52 0x064 MUX_M1 /* ISP_SCL0 */
53 0x068 MUX_M1 /* ISP_SDA0 */
59 0x05c MUX_M1 /* ISP_CLK1 */
60 0x06c MUX_M1 /* ISP_SCL1 */
61 0x070 MUX_M1 /* ISP_SDA1 */
[all …]
H A Dhikey970-pinctrl.dtsi42 0x064 MUX_M1 /* UART3_CTS_N */
43 0x068 MUX_M1 /* UART3_RTS_N */
44 0x06c MUX_M1 /* UART3_RXD */
45 0x070 MUX_M1 /* UART3_TXD */
51 0x074 MUX_M1 /* UART4_CTS_N */
52 0x078 MUX_M1 /* UART4_RTS_N */
53 0x07c MUX_M1 /* UART4_RXD */
54 0x080 MUX_M1 /* UART4_TXD */
60 0x05c MUX_M1 /* UART6_RXD */
61 0x060 MUX_M1 /* UART6_TXD */
[all …]
H A Dhikey-pinctrl.dtsi53 0xc MUX_M1 /* SD_CLK (IOMG003) */
54 0x10 MUX_M1 /* SD_CMD (IOMG004) */
55 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */
56 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */
57 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */
58 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */
74 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */
75 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */
76 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */
77 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */
[all …]
H A Dhi6220.dtsi424 &range 2 6 MUX_M1 /* gpio 8: [2..7] */
425 &range 8 8 MUX_M1 /* gpio 9: [0..7] */
426 &range 0 1 MUX_M1 /* gpio 10: [0] */
427 &range 16 7 MUX_M1 /* gpio 10: [1..7] */
428 &range 23 3 MUX_M1 /* gpio 11: [0..2] */
429 &range 28 5 MUX_M1 /* gpio 11: [3..7] */
430 &range 33 3 MUX_M1 /* gpio 12: [0..2] */
431 &range 43 5 MUX_M1 /* gpio 12: [3..7] */
432 &range 48 8 MUX_M1 /* gpio 13: [0..7] */
433 &range 56 8 MUX_M1 /* gpio 14: [0..7] */
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/hisilicon/
H A Dpinmux.c55 writel(MUX_M1, &pmx0->iomg[96]); /* UART3_CTS_N */ in hi6220_uart_config()
56 writel(MUX_M1, &pmx0->iomg[97]); /* UART3_RTS_N */ in hi6220_uart_config()
57 writel(MUX_M1, &pmx0->iomg[98]); /* UART3_RXD */ in hi6220_uart_config()
58 writel(MUX_M1, &pmx0->iomg[99]); /* UART3_TXD */ in hi6220_uart_config()
71 writel(MUX_M1, &pmx0->iomg[116]); /* UART4_CTS_N */ in hi6220_uart_config()
72 writel(MUX_M1, &pmx0->iomg[117]); /* UART4_RTS_N */ in hi6220_uart_config()
73 writel(MUX_M1, &pmx0->iomg[118]); /* UART4_RXD */ in hi6220_uart_config()
74 writel(MUX_M1, &pmx0->iomg[119]); /* UART4_TXD */ in hi6220_uart_config()
86 writel(MUX_M1, &pmx0->iomg[114]); /* UART5_RXD */ in hi6220_uart_config()
87 writel(MUX_M1, &pmx0->iomg[115]); /* UART5_TXD */ in hi6220_uart_config()
/openbmc/linux/include/dt-bindings/pinctrl/
H A Dhisi.h14 #define MUX_M1 1 macro
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dhisi.h22 #define MUX_M1 1 macro
/openbmc/u-boot/arch/arm/include/asm/arch-hi6220/
H A Dpinmux.h15 #define MUX_M1 1 macro