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Searched refs:MUX_GDL_SEL_SCLKMPLL (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos4_setup.h153 #define MUX_GDL_SEL_SCLKMPLL 0x0 macro
155 #define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)