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Searched refs:MUX_GATE (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt2712.c648 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31),
663 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents,
665 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
668 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_parents,
670 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,
672 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
678 MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel", dpilvds1_parents,
681 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_parents, 0x090, 24, 3, 31),
705 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents,
713 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
[all …]
H A Dclk-mt8135.c354 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
356 MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
357 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
360 MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
361 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
363 MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
374 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
377 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
381 MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
383 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
[all …]
H A Dclk-mt8173-topckgen.c537 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
539 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
542 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
546 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
561 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
566 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
568 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
569 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
570 MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents,
595 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents,
[all …]
H A Dclk-mt7622.c392 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
396 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
402 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
406 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
408 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
410 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
436 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
438 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
442 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
446 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
[all …]
H A Dclk-mt7629.c462 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
464 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
468 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
471 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
480 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
482 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
484 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
504 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
507 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
509 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents,
[all …]
H A Dclk-mt2701.c493 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
496 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
498 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
500 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
507 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
525 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
532 MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
548 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
550 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
578 MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
[all …]
H A Dclk-mt6797.c333 MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
337 MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),
342 MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,
346 MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
348 MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
350 MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
352 MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents,
364 MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
366 MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
374 MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents,
[all …]
H A Dclk-mtk.h141 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ macro
H A Dclk-mt8365.c393 MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents,
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c508 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
509 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
514 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
515 MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15),
520 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
521 MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15),
531 MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15),
539 MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7),
544 MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15),
553 MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7),
[all …]
H A Dclk-mt7629.c364 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
365 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
367 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
370 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
376 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
377 MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
391 MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31),
394 MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
398 MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
401 MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
[all …]
H A Dclk-mtk.h126 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ macro