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Searched refs:MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/include/dt-bindings/reset/
H A Dmt8195-resets.h77 #define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51 macro
/openbmc/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,ethdr.yaml173 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8195.dtsi3085 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,