Searched refs:MT76XX_MEMCTRL_BASE (Results 1 – 3 of 3) sorted by relevance
15 #define MT76XX_MEMCTRL_BASE (MT76XX_SYSCTL_BASE + 0x0300) macro22 #define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44)23 #define DDR_CFG2_REG (MT76XX_MEMCTRL_BASE + 0x48)24 #define DDR_CFG3_REG (MT76XX_MEMCTRL_BASE + 0x4c)25 #define DDR_CFG4_REG (MT76XX_MEMCTRL_BASE + 0x50)
93 writel(0x00007474, (void *)MT76XX_MEMCTRL_BASE + 0x64); in test_loop()104 (void *)MT76XX_MEMCTRL_BASE + 0x64); in test_loop()109 (void *)MT76XX_MEMCTRL_BASE + 0x64); in test_loop()167 clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4)); in ddr_calibrate()168 ddr_cfg2_reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x48); in ddr_calibrate()169 clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x48, in ddr_calibrate()183 reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x20); in ddr_calibrate()299 clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4)); in ddr_calibrate()300 writel(reg, (void *)MT76XX_MEMCTRL_BASE + 0x64); in ddr_calibrate()301 writel(ddr_cfg2_reg, (void *)MT76XX_MEMCTRL_BASE + 0x48); in ddr_calibrate()[all …]
67 li s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE)