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Searched refs:MT76XX_DYN_CFG0_REG (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mt7620/
H A Dddr_calibrate.c148 val = readl((void *)MT76XX_DYN_CFG0_REG); in ddr_calibrate()
156 val = readl((void *)MT76XX_DYN_CFG0_REG); in ddr_calibrate()
161 writel(val, (void *)MT76XX_DYN_CFG0_REG); in ddr_calibrate()
163 val = readl((void *)MT76XX_DYN_CFG0_REG); in ddr_calibrate()
H A Dmt76xx.h20 #define MT76XX_DYN_CFG0_REG (MT76XX_SYSCTL_BASE + 0x0440) macro
H A Dlowlevel_init.S93 la t0, MT76XX_DYN_CFG0_REG