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Searched refs:MSTP (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7343.c125 #define MSTP(_parent, _reg, _bit, _flags) \ macro
151 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
152 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
155 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
156 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
157 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
158 [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
159 [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
160 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
161 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
[all …]
H A Dclock-sh7366.c128 #define MSTP(_parent, _reg, _bit, _flags) \ macro
154 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
155 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
158 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
159 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
160 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
161 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
162 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
164 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
175 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-mstp-clocks.yaml7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
H A Drenesas,cpg-clocks.yaml17 the CPG Module Stop (MSTP) Clocks.
/openbmc/linux/drivers/clk/renesas/
H A DKconfig227 bool "MSTP clock support" if COMPILE_TEST
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr7s72100.dtsi407 /* MSTP clocks */