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Searched refs:MSR_TS0 (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/ppc/
H A Dcpu.h427 #define MSR_TS0 PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s) */ macro
476 FIELD(MSR, TS0, MSR_TS0, 1)
478 FIELD(MSR, TS, MSR_TS0, 2)
H A Dmachine.c188 | (1ULL << MSR_TS0) in cpu_pre_save()
H A Dcpu_init.c6363 (1ull << MSR_TS0) | in POWERPC_FAMILY()