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Searched refs:MSR_TM (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/ppc/
H A Dcpu_init.h51 (PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM))
H A Dhelper_regs.c180 if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { in hreg_compute_hflags_value()
H A Dcpu.h433 #define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */ macro
483 FIELD(MSR, TM, MSR_TM, 1)
H A Dtranslate.c1373 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); in spr_read_tm()
1379 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); in spr_write_tm()
1385 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); in spr_read_tm_upper32()
1391 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); in spr_write_tm_upper32()
H A Dcpu_init.c6379 (1ull << MSR_TM) | in POWERPC_FAMILY()
7262 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ in ppc_cpu_reset_hold()