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Searched refs:MSR_TM (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/ppc/
H A Dcpu_init.h51 (PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM))
H A Dcpu.h437 #define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */ macro
512 FIELD(MSR, TM, MSR_TM, 1)
H A Dcpu_init.c6366 (1ull << MSR_TM) | in POWERPC_FAMILY()
7271 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ in ppc_cpu_reset_hold()