Searched refs:MSR_IPE (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/target/ppc/ | ||
| H A D | cpu.h | 479 #define MSR_IPE PPC_BIT_NR(55) /* Imprecise Mode Enable (PPE42) */ macro |
| H A D | cpu_init.c | 2294 (1ull << MSR_IPE) | in ppe42_class_common_init() |