Searched refs:MSR_IA32_APICBASE_ENABLE (Results 1 – 6 of 6) sorted by relevance
323 if (!(val & MSR_IA32_APICBASE_ENABLE) && in apic_set_base_check()329 if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) && in apic_set_base_check()331 (val & MSR_IA32_APICBASE_ENABLE) && in apic_set_base_check()337 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) && in apic_set_base_check()339 (val & MSR_IA32_APICBASE_ENABLE) && in apic_set_base_check()354 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); in apic_set_base()355 if (!(val & MSR_IA32_APICBASE_ENABLE)) { in apic_set_base()356 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; in apic_set_base()362 if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) && in apic_set_base()363 (val & MSR_IA32_APICBASE_ENABLE)) { in apic_set_base()[all …]
75 return s->apicbase & MSR_IA32_APICBASE_ENABLE; in cpu_is_apic_enabled()257 s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; in apic_reset_common()
72 msr.lo |= MSR_IA32_APICBASE_ENABLE; in enable_lapic()85 msr.lo &= ~MSR_IA32_APICBASE_ENABLE; in disable_lapic()
59 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; in x86_cpu_apic_create()
386 #define MSR_IA32_APICBASE_ENABLE (1<<11) macro390 (~(uint64_t)(MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE \
372 #define MSR_IA32_APICBASE_ENABLE (1<<11) macro