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Searched refs:MSR_HV (Results 1 – 25 of 27) sorted by relevance

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/openbmc/linux/arch/powerpc/kernel/
H A Dcpu_setup_power.c22 if (msr & MSR_HV) in init_hvmode_206()
156 if (!(msr & MSR_HV)) in __restore_cpu_power7()
192 if (!(msr & MSR_HV)) in __restore_cpu_power8()
231 if (!(msr & MSR_HV)) in __restore_cpu_power9()
276 if (!(msr & MSR_HV)) in __restore_cpu_power10()
H A Dpaca.c232 if (mfmsr() & MSR_HV) in setup_paca()
H A Ddt_cpu_ftrs.c119 hv_mode = !!(mfmsr() & MSR_HV); in cpufeatures_setup_cpu()
934 if (!(mfmsr() & MSR_HV)) { in process_cpufeatures_node()
H A Dsetup_64.c372 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && (mfmsr() & MSR_HV)) in early_setup()
H A Dtraps.c405 if (!(regs->msr & MSR_HV)) in hv_nmi_check_nonrecoverable()
H A Dprocess.c1471 {MSR_HV, "HV"},
/openbmc/linux/tools/testing/selftests/powerpc/pmu/sampling_tests/
H A Dmmcr2_fcs_fch_test.c23 is_hv = !!(uctx->uc_mcontext.gp_regs[PT_MSR] & MSR_HV); in sig_usr2_handler()
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg.h71 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ macro
76 #define MSR_HV 0 macro
134 #define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_HV)
137 #define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
140 #define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
H A Dkvm_book3s_64.h584 msr &= ~MSR_HV; in sanitize_msr()
/openbmc/linux/drivers/tty/hvc/
H A Dhvc_vio.c442 if (mfmsr() & MSR_HV) in udbg_init_debug_lpar()
459 if (mfmsr() & MSR_HV) in udbg_init_debug_lpar_hvsi()
/openbmc/linux/tools/testing/selftests/powerpc/include/
H A Dreg.h98 #define MSR_HV (1ul << 60) /* Hypervisor state */ macro
/openbmc/qemu/target/ppc/
H A Dhelper_regs.c68 hv = !!(env->msr & (1ull << MSR_HV)); in hreg_check_bhrb_enable()
188 if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { in hreg_compute_hflags_value()
227 dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0; in hreg_compute_hflags_value()
H A Dcpu.h426 #define MSR_HV PPC_BIT_NR(3) /* hypervisor state hflags */ macro
471 FIELD(MSR, HV, MSR_HV, 1)
649 #define MSR_HVB (1ULL << MSR_HV)
H A Dexcp_helper.c3241 !(env->msr & ((target_ulong)1 << MSR_HV))); in ppc_cpu_debug_check_breakpoint()
3244 (env->msr & ((target_ulong)1 << MSR_HV))); in ppc_cpu_debug_check_breakpoint()
3270 } else if ((env->msr & ((target_ulong)1 << MSR_HV)) && !hv) { in ppc_cpu_debug_check_watchpoint()
H A Dcpu_init.c6347 (1ull << MSR_HV) | in POWERPC_FAMILY()
6541 (1ull << MSR_HV) | in POWERPC_FAMILY()
6722 (1ull << MSR_HV) | in POWERPC_FAMILY()
/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_emulate.c148 if (kvmppc_get_msr(vcpu) & MSR_HV) in kvmppc_emulate_treclaim()
223 if (guest_msr & MSR_HV) in kvmppc_emulate_tabort()
509 if (kvmppc_get_msr(vcpu) & MSR_HV) in kvmppc_core_emulate_op_pr()
752 (mfmsr() & MSR_HV)) in kvmppc_core_emulate_mtspr_pr()
H A Dbook3s_hv_builtin.c506 msr = (msr | MSR_ME) & ~MSR_HV; in kvmppc_set_msr_hv()
H A Dbook3s_hv_p9_entry.c558 WARN_ON_ONCE(vcpu->arch.shregs.msr & MSR_HV); in kvmhv_vcpu_entry_p9()
645 mtspr(SPRN_HSRR1, (vcpu->arch.shregs.msr & ~MSR_HV) | MSR_ME); in kvmhv_vcpu_entry_p9()
H A Dbook3s_pr.c249 smsr |= MSR_HV; in kvmppc_recalc_shadow_msr()
478 msr = (msr & ~MSR_HV) | MSR_ME; in kvmppc_set_msr_pr()
584 if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) && in kvmppc_set_pvr_pr()
H A Dbook3s_hv_nested.c370 vcpu->arch.shregs.msr = (vcpu->arch.regs.msr | MSR_ME) & ~MSR_HV; in kvmhv_enter_nested_guest()
/openbmc/linux/arch/powerpc/mm/
H A Dinit_64.c623 bool hvmode = !!(mfmsr() & MSR_HV); in mmu_early_init_devtree()
/openbmc/linux/arch/powerpc/platforms/pseries/
H A Dras.c497 MSR_ILE|MSR_HV|MSR_SF)) == (MSR_DR|MSR_SF)) { in pSeries_system_reset_exception()
/openbmc/linux/arch/powerpc/perf/
H A Dcore-book3s.c261 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) in perf_flags_from_msr()
2548 #ifdef MSR_HV in register_power_pmu()
2552 if (mfmsr() & MSR_HV) in register_power_pmu()
/openbmc/linux/arch/powerpc/xmon/
H A Dxmon.c2031 if (!(mfmsr() & MSR_HV)) in dump_206_sprs()
2082 if (!(msr & MSR_HV)) in dump_207_sprs()
2100 bool hv = mfmsr() & MSR_HV; in dump_300_sprs()
/openbmc/linux/drivers/misc/cxl/
H A Dcxl.h200 #define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */

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