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Searched refs:MSR_CE (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/arch/powerpc/platforms/44x/
H A Didle.c23 mtmsr(msr_save|MSR_WE|MSR_EE|MSR_CE|MSR_DE); in ppc44x_idle()
/openbmc/u-boot/include/
H A Dppc_asm.tmpl236 MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
244 MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
275 MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
283 MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
/openbmc/linux/arch/powerpc/include/asm/
H A Dprobes.h80 regs_set_return_msr(regs, regs->msr & ~MSR_CE); in enable_single_step()
H A Dreg_booke.h41 #define MSR_ (MSR_ME | MSR_RI | MSR_CE)
46 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
49 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
H A Dreg.h93 #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */ macro
/openbmc/linux/arch/powerpc/platforms/4xx/
H A Dcpm.c85 mtmsr(msr_save|MSR_WE|MSR_EE|MSR_CE|MSR_DE); in cpm_idle_wait()
/openbmc/linux/arch/powerpc/kvm/
H A Dbookehv_interrupts.S91 oris r8, r6, MSR_CE@h
107 oris r7, r7, MSR_CE@h
H A Dbooke.c471 msr_mask = MSR_CE | MSR_ME | MSR_DE; in kvmppc_booke_irqprio_deliver()
477 allowed = vcpu->arch.shared->msr & MSR_CE; in kvmppc_booke_irqprio_deliver()
495 msr_mask = MSR_CE | MSR_ME | MSR_DE; in kvmppc_booke_irqprio_deliver()
/openbmc/qemu/target/ppc/
H A Dcpu_init.c2175 (1ull << MSR_CE) |
2246 (1ull << MSR_CE) |
2285 (1ull << MSR_CE) |
2337 (1ull << MSR_CE) |
2407 (1ull << MSR_CE) |
2446 (1ull << MSR_CE) |
2780 (1ull << MSR_CE) | in POWERPC_FAMILY()
3058 (1ull << MSR_CE) | in POWERPC_FAMILY()
3102 (1ull << MSR_CE) | in POWERPC_FAMILY()
3147 (1ull << MSR_CE) | in POWERPC_FAMILY()
[all …]
H A Dcpu.h444 #define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x */ macro
494 FIELD(MSR, CE, MSR_CE, 1)
/openbmc/linux/arch/powerpc/kernel/
H A Dhead_40x.S131 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)) /* re-enable MMU */
H A Dhead_booke.h205 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
H A Dprocess.c1476 {MSR_CE, "CE"},
/openbmc/linux/arch/powerpc/platforms/83xx/
H A Dsuspend-asm.S224 rlwinm r4, r4, 0, ~MSR_CE
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dcpu_init.c1021 msr &= ~(MSR_ME|MSR_CE); in arch_preboot_os()
H A Dstart.S1229 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1230 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h25 #define MSR_CE (1<<17) /* Critical Interrupt Enable */ macro