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Searched refs:MSECCFG_MMWP (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dpmp.h44 MSECCFG_MMWP = 1 << 1, enumerator
88 #define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
H A Dpmp.c593 val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); in mseccfg_csr_write()
594 if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) { in mseccfg_csr_write()
598 val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB); in mseccfg_csr_write()