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Searched refs:MSCC_F_MII_STATUS_MIIM_STAT_BUSY (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_devcpu_gcb_miim_regs.h15 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) (x ? BIT(3) : 0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_devcpu_gcb_miim_regs.h13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_devcpu_gcb_miim_regs.h13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_devcpu_gcb_miim_regs.h13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_devcpu_gcb_miim_regs.h13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) macro
/openbmc/u-boot/arch/mips/mach-mscc/
H A Dphy.c41 } while (data & MSCC_F_MII_STATUS_MIIM_STAT_BUSY(1)); in mscc_phy_rd_wr()