Searched refs:MSCC_DDR_TO (Results 1 – 3 of 3) sorted by relevance
511 byte = __raw_readb((void __iomem *)MSCC_DDR_TO + bytelane + in look_for()550 byte = __raw_readb((void __iomem *)MSCC_DDR_TO + bytelane + in look_past()619 byte = __raw_readb((void __iomem *)MSCC_DDR_TO); in hal_vcoreiii_init_dqs()620 byte = __raw_readb((void __iomem *)(MSCC_DDR_TO + 1)); in hal_vcoreiii_init_dqs()635 __raw_writel(~i, (void __iomem *)(MSCC_DDR_TO + (i * 4))); in dram_check()636 if (__raw_readl((void __iomem *)(MSCC_DDR_TO + (i * 4))) != ~i) in dram_check()676 register u32 byte = __raw_readb((void __iomem *)MSCC_DDR_TO); in look_for()724 __raw_writel(~i, (void __iomem *)(MSCC_DDR_TO + (i * 4))); in dram_check()726 if (__raw_readl((void __iomem *)(MSCC_DDR_TO + (i * 4))) != ~i) in dram_check()834 __raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO)); in hal_vcoreiii_wait_memctl()[all …]
38 #define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */ macro
71 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()