Searched refs:MSCC_ANA_IP1_FLOW_MASK_UPPER_MID (Results 1 – 2 of 2) sorted by relevance
333 #define MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 6) macro
596 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(0), in vsc85xx_ip_cmp1_init()