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Searched refs:MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h10962 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h24262 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h20348 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_1_0_sh_mask.h18976 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h40213 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h15189 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h22675 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h20692 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h23433 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h55898 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h47215 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h23416 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h54366 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h15186 #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT … macro