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Searched refs:MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h10804 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h24122 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h40073 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h20188 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h15039 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_1_0_sh_mask.h18812 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h22535 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h20552 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h23293 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h47075 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h55758 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h54226 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h23256 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h15036 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT … macro