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Searched refs:MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h10801 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h24119 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h20185 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h40070 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h15036 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h22532 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h20549 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h23290 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h55755 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h47072 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h23253 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h54223 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h15033 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro