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Searched refs:MO_64 (Results 1 – 25 of 56) sorted by relevance

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/openbmc/qemu/target/hexagon/
H A Dgen_tcg_hvx.h52 tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
68 tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
84 tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
100 tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
117 tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
128 tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \
132 tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \
137 tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \
139 tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), VuV_off, \
151 tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \
[all …]
H A Dgenptr.c389 ctx->mem_idx, MO_64); in gen_store_conditional8()
1206 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, in gen_log_vreg_write()
1210 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, in gen_log_vreg_write()
1268 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMVector), sizeof(MMVector)); in gen_vreg_store()
1270 tcg_gen_gvec_dup_imm(MO_64, maskoff, sizeof(MMQReg), sizeof(MMQReg), ~0LL); in gen_vreg_store()
1285 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMVector), sizeof(MMVector)); in gen_vreg_masked_store()
1287 tcg_gen_gvec_mov(MO_64, maskoff, bitsoff, sizeof(MMQReg), sizeof(MMQReg)); in gen_vreg_masked_store()
1289 tcg_gen_gvec_not(MO_64, maskoff, maskoff, in gen_vreg_masked_store()
H A Dtranslate.c522 tcg_gen_gvec_mov(MO_64, VdV_off, in gen_start_packet()
535 tcg_gen_gvec_mov(MO_64, VdV_off, in gen_start_packet()
805 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); in gen_commit_hvx()
820 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); in gen_commit_hvx()
/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_vec.c.inc346 TRANS(vadd_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_add)
350 TRANS(xvadd_d, LASX, gvec_xxx, MO_64, tcg_gen_gvec_add)
401 TRANS(vsub_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_sub)
405 TRANS(xvsub_d, LASX, gvec_xxx, MO_64, tcg_gen_gvec_sub)
415 TRANS(vaddi_du, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_addi)
419 TRANS(vsubi_du, LSX, gvec_subi, MO_64)
423 TRANS(xvaddi_du, LASX, gvec_xx_i, MO_64, tcg_gen_gvec_addi)
427 TRANS(xvsubi_du, LASX, gvec_xsubi, MO_64)
432 TRANS(vneg_d, LSX, gvec_vv, MO_64, tcg_gen_gvec_neg)
436 TRANS(xvneg_d, LASX, gvec_xx, MO_64, tcg_gen_gvec_neg)
[all …]
/openbmc/qemu/tcg/
H A Dtcg-op-gvec.c394 case MO_64: in uint64_t()
434 case MO_64: in tcg_gen_dup_i64()
546 assert(vece <= (in_32 ? MO_32 : MO_64)); in do_dup()
565 && (in_64 == NULL || vece == MO_64))); in do_dup()
607 if (vece == MO_64 in do_dup()
667 if (vece == MO_64) { in do_dup()
1720 tcg_debug_assert(vece <= MO_64); in tcg_gen_gvec_dup_i64()
1728 if (vece <= MO_64) { in tcg_gen_gvec_dup_mem()
1957 .vece = MO_64 }, in tcg_gen_gvec_add()
1960 tcg_debug_assert(vece <= MO_64); in tcg_gen_gvec_add()
[all …]
H A Dtcg-op-ldst.c68 case MO_64: in tcg_canonicalize_memop()
346 if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { in tcg_gen_qemu_ld_i64_int()
363 if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) { in tcg_gen_qemu_ld_i64_int()
390 case MO_64: in tcg_gen_qemu_ld_i64_int()
403 tcg_debug_assert((memop & MO_SIZE) <= MO_64); in tcg_gen_qemu_ld_i64_chk()
414 if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { in tcg_gen_qemu_st_i64_int()
432 case MO_64: in tcg_gen_qemu_st_i64_int()
460 tcg_debug_assert((memop & MO_SIZE) <= MO_64); in tcg_gen_qemu_st_i64_chk()
499 mop_1 = (mop_1 & ~MO_SIZE) | MO_64; in canonicalize_memop_i128_as_i64()
871 WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le)
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dtranslate-sme.c76 if (HOST_BIG_ENDIAN && esz < MO_64) { in get_tile_rowcol()
290 TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d) in TRANS_FEAT()
291 TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d) in TRANS_FEAT()
363 MO_64, FPST_FPCR, gen_helper_sme_fmopa_d)
372 TRANS_FEAT(SMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_smopa_d)
373 TRANS_FEAT(UMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_umopa_d)
374 TRANS_FEAT(SUMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_sumopa_d)
375 TRANS_FEAT(USMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_usmopa_d)
H A Dtranslate-neon.c113 case MO_64: in neon_store_element64()
1143 read_neon_element64(rm1, a->vm, 0, MO_64); in DO_2SH()
1144 read_neon_element64(rm2, a->vm, 1, MO_64); in DO_2SH()
1335 write_neon_element64(tmp, a->vd, 0, MO_64); in DO_2SN_64()
1342 write_neon_element64(tmp, a->vd, 1, MO_64); in DO_2SN_64()
1447 fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size); in DO_FP_2SH()
1454 tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c); in gen_VMOV_1r()
1546 write_neon_element64(rn0_64, a->vd, 0, MO_64); in do_prewiden_3d()
1549 write_neon_element64(rn1_64, a->vd, 1, MO_64); in do_prewiden_3d()
1618 read_neon_element64(rn_64, a->vn, 0, MO_64); in DO_PREWIDEN()
[all …]
H A Dgengvec64.c46 .vece = MO_64, in gen_gvec_rax1()
121 .vece = MO_64 } in gen_gvec_xar()
159 .vece = MO_64, in gen_gvec_eor3()
185 .vece = MO_64, in gen_gvec_bcax()
270 .vece = MO_64 }, in gen_gvec_suqadd_qc()
365 .vece = MO_64 }, in gen_gvec_usqadd_qc()
H A Dgengvec.c171 .vece = MO_64 }, in gen_gvec_ssra()
247 .vece = MO_64, }, in gen_gvec_usra()
354 .vece = MO_64 }, in gen_gvec_srshr()
445 .vece = MO_64 }, in gen_gvec_srsra()
548 .vece = MO_64 }, in gen_gvec_urshr()
658 .vece = MO_64 }, in gen_gvec_ursra()
742 .vece = MO_64 }, in gen_gvec_sri()
829 .vece = MO_64 }, in gen_gvec_sli()
933 .vece = MO_64 }, in gen_gvec_mla()
965 .vece = MO_64 }, in gen_gvec_mls()
[all …]
H A Dtranslate-a64.c598 return vec_reg_offset(s, regno, 1, MO_64); in fp_reg_hi_offset()
611 tcg_gen_ld_i64(v, tcg_env, fp_reg_offset(s, reg, MO_64)); in read_fp_dreg()
636 unsigned ofs = fp_reg_offset(s, rd, MO_64); in clear_vec_high()
640 tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz); in clear_vec_high()
645 unsigned ofs = fp_reg_offset(s, reg, MO_64); in write_fp_dreg()
1031 tcg_gen_ld_i64(tmplo, tcg_env, fp_reg_offset(s, srcidx, MO_64)); in do_fp_st()
1066 tcg_gen_st_i64(tmplo, tcg_env, fp_reg_offset(s, destidx, MO_64)); in do_fp_ld()
1110 case MO_64: in read_vec_element()
1111 case MO_64|MO_SIGN: in read_vec_element()
1160 case MO_64: in write_vec_element()
[all …]
H A Dsve_helper.c5865 DO_LD1_1(ld1bdu, MO_64) in DO_LD1_1()
5866 DO_LD1_1(ld1bds, MO_64) in DO_LD1_1()
5871 DO_LD1_2(ld1hdu, MO_64, MO_16) in DO_LD1_1()
5872 DO_LD1_2(ld1hds, MO_64, MO_16) in DO_LD1_1()
5875 DO_LD1_2(ld1sdu, MO_64, MO_32) in DO_LD1_1()
5876 DO_LD1_2(ld1sds, MO_64, MO_32) in DO_LD1_1()
5878 DO_LD1_2(ld1dd, MO_64, MO_64) in DO_LD1_1()
5935 DO_LDN_2(2, dd, MO_64)
5936 DO_LDN_2(3, dd, MO_64)
5937 DO_LDN_2(4, dd, MO_64)
[all …]
H A Dtranslate-sve.c482 tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word); in do_dupi_z()
491 gvec_fn(MO_64, pred_full_reg_offset(s, rd), in gen_gvec_fn_ppp()
616 .vece = MO_64, in gen_bsl1n()
660 .vece = MO_64, in gen_bsl2n()
689 .vece = MO_64, in gen_nbsl()
1640 tcg_gen_gvec_dup_imm(MO_64, ofs, oprsz, maxsz, word); in do_predset()
1859 case MO_64: in do_sat_addsub_vec()
2012 return gen_gvec_fn_zzi(s, gvec_fn, MO_64, a->rd, a->rn, imm); in do_zz_dbm()
2187 tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0); in trans_DUP_x()
2218 tcg_gen_ld_i64(t, tcg_env, vec_reg_offset(s, a->rm, 0, MO_64)); in trans_INSR_f()
[all …]
/openbmc/qemu/include/exec/
H A Dmemop.h21 MO_64 = 3, enumerator
116 MO_UQ = MO_64,
121 MO_SQ = MO_SIGN | MO_64,
H A Dtarget_long.h39 #define MO_TL MO_64
/openbmc/qemu/target/ppc/translate/
H A Dvsx-impl.c.inc739 TRANS(XVABSDP, do_vsx_msb_op, MO_64, do_xvabs_vec, do_xvabsdp_i64)
740 TRANS(XVNABSDP, do_vsx_msb_op, MO_64, do_xvnabs_vec, do_xvnabsdp_i64)
741 TRANS(XVNEGDP, do_vsx_msb_op, MO_64, do_xvneg_vec, do_xvnegdp_i64)
783 .vece = MO_64
797 TRANS(XVCPSGNDP, do_xvcpsgn, MO_64)
1167 TRANS_FLAGS2(VSX, XVTSTDCDP, do_xvtstdc, MO_64)
1588 TRANS_FLAGS2(VSX, XXLAND, do_logical_op, MO_64, tcg_gen_gvec_and);
1589 TRANS_FLAGS2(VSX, XXLANDC, do_logical_op, MO_64, tcg_gen_gvec_andc);
1590 TRANS_FLAGS2(VSX, XXLOR, do_logical_op, MO_64, tcg_gen_gvec_or);
1591 TRANS_FLAGS2(VSX, XXLXOR, do_logical_op, MO_64, tcg_gen_gvec_xor);
[all …]
H A Dvmx-impl.c.inc348 GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
352 GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
695 TRANS_FLAGS2(ALTIVEC_207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv);
700 TRANS_FLAGS2(ALTIVEC_207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv);
705 TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
710 TRANS_FLAGS2(ALTIVEC_207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv)
713 TRANS_FLAGS(ALTIVEC, VAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_and);
714 TRANS_FLAGS(ALTIVEC, VANDC, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_andc);
715 TRANS_FLAGS(ALTIVEC, VOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_or);
716 TRANS_FLAGS(ALTIVEC, VXOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_xor);
[all …]
/openbmc/qemu/target/s390x/tcg/
H A Dvec.h85 case MO_64: in s390_vec_read_element()
133 case MO_64: in s390_vec_write_element()
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dspecial_helper.c157 MO_64, MEMTXATTRS_UNSPECIFIED); in helper_cache()
161 MO_64, MEMTXATTRS_UNSPECIFIED); in helper_cache()
/openbmc/qemu/target/i386/tcg/
H A Demit.c.inc113 case MO_64:
129 case MO_64:
173 case MO_64:
223 case MO_64:
371 tcg_gen_gvec_dup_imm(MO_64,
465 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, src_ofs, vec_len, vec_len);
470 case MO_64:
824 UNARY_INT_GVEC(VPBROADCASTQ, tcg_gen_gvec_dup_mem, MO_64)
840 BINARY_INT_GVEC(PADDQ, tcg_gen_gvec_add, MO_64)
845 BINARY_INT_GVEC(PAND, tcg_gen_gvec_and, MO_64)
[all …]
H A Dtranslate.c425 return ot == MO_16 ? MO_16 : MO_64; in mo_pushpop()
434 return CODE64(s) ? MO_64 : SS32(s) ? MO_32 : MO_16; in mo_stacksize()
468 case MO_64: in gen_op_deposit_reg_v()
627 case MO_64: in gen_lea_v_seg_dest()
663 if (aflag == MO_64) { in gen_lea_v_seg_dest()
1442 target_ulong mask = (ot == MO_64 ? 63 : 31); in gen_shiftd_rm_T1()
1582 case MO_64: in gen_lea_modrm_0()
1779 case MO_64: in insn_get_addr()
1802 case MO_64: in insn_get()
1827 case MO_64: in insn_get_signed()
[all …]
/openbmc/qemu/accel/tcg/
H A Dldst_atomicity.c.inc504 if (atmax == MO_64) {
567 case MO_64:
575 case -MO_64:
1030 case MO_64:
1079 case MO_64:
1086 case -MO_64:
1106 case 8: /* atmax MO_64 */
H A Dldst_common.c.inc39 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64);
106 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64);
175 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64);
234 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64);
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc46 case MO_64:
304 ret &= (eew != MO_64);
439 (s->sew < MO_64) &&
467 (s->sew < MO_64) &&
720 GEN_VEXT_TRANS(vle64_v, MO_64, r2nfvm, ld_us_op, ld_us_check)
757 GEN_VEXT_TRANS(vse64_v, MO_64, r2nfvm, st_us_op, st_us_check)
869 GEN_VEXT_TRANS(vlse64_v, MO_64, rnfvm, ld_stride_op, ld_stride_check)
903 GEN_VEXT_TRANS(vsse64_v, MO_64, rnfvm, st_stride_op, st_stride_check)
990 GEN_VEXT_TRANS(vlxei64_v, MO_64, rnfvm, ld_index_op, ld_index_check)
1042 GEN_VEXT_TRANS(vsxei64_v, MO_64, rnfvm, st_index_op, st_index_check)
[all …]
/openbmc/qemu/tcg/i386/
H A Dtcg-target.c.inc973 case MO_64:
992 case MO_64:
1029 if (TCG_TARGET_REG_BITS == 32 && vece < MO_64) {
2465 case MO_64:
3467 tcg_out_dup_vec(s, type, MO_64, a0, a0);
3504 if (vece == MO_64) {
3513 if (vece == MO_64) {
3910 case MO_64:
3915 * We can emulate this for MO_64, but it does not pay off
3930 case MO_64:
[all …]

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