/openbmc/linux/arch/arm/kernel/ |
H A D | phys2virt.S | 77 @ In the non-LPAE case, all patchable instructions are MOVW 105 ubfx r6, r6, #21, #8 @ put bits 28:21 into the MOVW imm8 field 106 bfi r6, r3, #12, #3 @ put bits 31:29 into the MOVW imm3 field 113 tst ip, #0x200 @ MOVW has bit 9 set, MVN has it clear 114 bne 0f @ skip to MOVW handling (Z flag is clear) 126 orrne ip, r6 @ Z flag clear -> MOVW -> patch in low bits 172 @ instruction if the offset is negative. We can distinguish MOVW 179 @ MOVW | cond | 0 0 1 1 0 0 0 0 | imm4 | Rd | imm12 | 192 tst ip, #0xc00000 @ MOVW has bits 23:22 clear 195 orreq ip, ip, r6, lsl #4 @ MOVW -> mask in offset bits 31-24 [all …]
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/openbmc/qemu/linux-user/sh4/ |
H A D | signal.c | 73 #define MOVW(n) (0x9300|((n)-2)) /* Move mem word at PC+n to R3 */ macro 338 __put_user(MOVW(2), &tramp[0]); in setup_sigtramp() 343 __put_user(MOVW(2), &tramp[3]); in setup_sigtramp()
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/openbmc/linux/arch/sh/kernel/ |
H A D | signal_32.c | 54 #define MOVW(n) (0x9300|((n)-2)) /* Move mem word at PC+n to R3 */ macro 296 err |= __put_user(MOVW(7), &frame->retcode[0]); in setup_frame() 366 err |= __put_user(MOVW(7), &frame->retcode[0]); in setup_rt_frame()
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/openbmc/qemu/target/avr/ |
H A D | insn.decode | 128 MOVW 0000 0001 .... .... &rd_rr rd=%rd_d rr=%rr_d
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H A D | disas.c | 186 INSN(MOVW, "r%d:r%d, r%d:r%d", a->rd + 1, a->rd, a->rr + 1, a->rr)
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/openbmc/qemu/target/arm/tcg/ |
H A D | a32.decode | 82 MOVW .... 0011 0000 .... .... ............ @mov16
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H A D | t32.decode | 231 MOVW 1111 0.10 0100 .... 0 ... .... ........ @mov16
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/openbmc/qemu/tcg/arm/ |
H A D | tcg-target.c.inc | 1453 * Do this in 2-4 insns. Use MOVW for v7, if possible,
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/openbmc/qemu/tests/tcg/i386/ |
H A D | x86.csv | 1202 "MOV moffs16, AX","MOVW AX, moffs16","movw AX, moffs16","A3 cm","V","V","","operand16","w,r","Y","1… 1203 "MOV r/m16, Sreg","MOVW Sreg, r/m16","movw Sreg, r/m16","8C /r","V","V","","operand16","w,r","Y","1… 1204 "MOV r/m16, imm16","MOVW imm16, r/m16","movw imm16, r/m16","C7 /0 iw","V","V","","operand16","w,r",… 1205 "MOV r16op, imm16u","MOVW imm16u, r16op","movw imm16u, r16op","B8+rw iw","V","V","","operand16","w,… 1206 "MOV AX, moffs16","MOVW moffs16, AX","movw moffs16, AX","A1 cm","V","V","","operand16","w,r","Y","1… 1207 "MOV Sreg, r/m16","MOVW r/m16, Sreg","movw r/m16, Sreg","8E /r","V","V","","","w,r","Y","16" 1208 "MOV r16, r/m16","MOVW r/m16, r16","movw r/m16, r16","8B /r","V","V","","operand16","w,r","Y","16" 1209 "MOV r/m16, r16","MOVW r16, r/m16","movw r16, r/m16","89 /r","V","V","","operand16","w,r","Y","16"
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