1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 4 */ 5 6 #ifndef __REGS_MMC_H__ 7 #define __REGS_MMC_H__ 8 9 #define MMC0_BASE 0x41100000 10 #define MMC1_BASE 0x42000000 11 12 int pxa_mmc_register(int card_index); 13 14 struct pxa_mmc_regs { 15 uint32_t strpcl; 16 uint32_t stat; 17 uint32_t clkrt; 18 uint32_t spi; 19 uint32_t cmdat; 20 uint32_t resto; 21 uint32_t rdto; 22 uint32_t blklen; 23 uint32_t nob; 24 uint32_t prtbuf; 25 uint32_t i_mask; 26 uint32_t i_reg; 27 uint32_t cmd; 28 uint32_t argh; 29 uint32_t argl; 30 uint32_t res; 31 uint32_t rxfifo; 32 uint32_t txfifo; 33 }; 34 35 /* MMC_STRPCL */ 36 #define MMC_STRPCL_STOP_CLK (1 << 0) 37 #define MMC_STRPCL_START_CLK (1 << 1) 38 39 /* MMC_STAT */ 40 #define MMC_STAT_END_CMD_RES (1 << 13) 41 #define MMC_STAT_PRG_DONE (1 << 12) 42 #define MMC_STAT_DATA_TRAN_DONE (1 << 11) 43 #define MMC_STAT_CLK_EN (1 << 8) 44 #define MMC_STAT_RECV_FIFO_FULL (1 << 7) 45 #define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6) 46 #define MMC_STAT_RES_CRC_ERROR (1 << 5) 47 #define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4) 48 #define MMC_STAT_CRC_READ_ERROR (1 << 3) 49 #define MMC_STAT_CRC_WRITE_ERROR (1 << 2) 50 #define MMC_STAT_TIME_OUT_RESPONSE (1 << 1) 51 #define MMC_STAT_READ_TIME_OUT (1 << 0) 52 53 /* MMC_CLKRT */ 54 #define MMC_CLKRT_20MHZ 0 55 #define MMC_CLKRT_10MHZ 1 56 #define MMC_CLKRT_5MHZ 2 57 #define MMC_CLKRT_2_5MHZ 3 58 #define MMC_CLKRT_1_25MHZ 4 59 #define MMC_CLKRT_0_625MHZ 5 60 #define MMC_CLKRT_0_3125MHZ 6 61 62 /* MMC_SPI */ 63 #define MMC_SPI_EN (1 << 0) 64 #define MMC_SPI_CS_EN (1 << 2) 65 #define MMC_SPI_CS_ADDRESS (1 << 3) 66 #define MMC_SPI_CRC_ON (1 << 1) 67 68 /* MMC_CMDAT */ 69 #define MMC_CMDAT_SD_4DAT (1 << 8) 70 #define MMC_CMDAT_MMC_DMA_EN (1 << 7) 71 #define MMC_CMDAT_INIT (1 << 6) 72 #define MMC_CMDAT_BUSY (1 << 5) 73 #define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT) 74 #define MMC_CMDAT_STREAM (1 << 4) 75 #define MMC_CMDAT_WRITE (1 << 3) 76 #define MMC_CMDAT_DATA_EN (1 << 2) 77 #define MMC_CMDAT_R0 0 78 #define MMC_CMDAT_R1 1 79 #define MMC_CMDAT_R2 2 80 #define MMC_CMDAT_R3 3 81 82 /* MMC_RESTO */ 83 #define MMC_RES_TO_MAX_MASK 0x7f 84 85 /* MMC_RDTO */ 86 #define MMC_READ_TO_MAX_MASK 0xffff 87 88 /* MMC_BLKLEN */ 89 #define MMC_BLK_LEN_MAX_MASK 0x3ff 90 91 /* MMC_PRTBUF */ 92 #define MMC_PRTBUF_BUF_PART_FULL (1 << 0) 93 94 /* MMC_I_MASK */ 95 #define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6) 96 #define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5) 97 #define MMC_I_MASK_CLK_IS_OFF (1 << 4) 98 #define MMC_I_MASK_STOP_CMD (1 << 3) 99 #define MMC_I_MASK_END_CMD_RES (1 << 2) 100 #define MMC_I_MASK_PRG_DONE (1 << 1) 101 #define MMC_I_MASK_DATA_TRAN_DONE (1 << 0) 102 #define MMC_I_MASK_ALL 0x7f 103 104 105 /* MMC_I_REG */ 106 #define MMC_I_REG_TXFIFO_WR_REQ (1 << 6) 107 #define MMC_I_REG_RXFIFO_RD_REQ (1 << 5) 108 #define MMC_I_REG_CLK_IS_OFF (1 << 4) 109 #define MMC_I_REG_STOP_CMD (1 << 3) 110 #define MMC_I_REG_END_CMD_RES (1 << 2) 111 #define MMC_I_REG_PRG_DONE (1 << 1) 112 #define MMC_I_REG_DATA_TRAN_DONE (1 << 0) 113 114 /* MMC_CMD */ 115 #define MMC_CMD_INDEX_MAX 0x6f 116 117 #define MMC_R1_IDLE_STATE 0x01 118 #define MMC_R1_ERASE_STATE 0x02 119 #define MMC_R1_ILLEGAL_CMD 0x04 120 #define MMC_R1_COM_CRC_ERR 0x08 121 #define MMC_R1_ERASE_SEQ_ERR 0x01 122 #define MMC_R1_ADDR_ERR 0x02 123 #define MMC_R1_PARAM_ERR 0x04 124 125 #define MMC_R1B_WP_ERASE_SKIP 0x0002 126 #define MMC_R1B_ERR 0x0004 127 #define MMC_R1B_CC_ERR 0x0008 128 #define MMC_R1B_CARD_ECC_ERR 0x0010 129 #define MMC_R1B_WP_VIOLATION 0x0020 130 #define MMC_R1B_ERASE_PARAM 0x0040 131 #define MMC_R1B_OOR 0x0080 132 #define MMC_R1B_IDLE_STATE 0x0100 133 #define MMC_R1B_ERASE_RESET 0x0200 134 #define MMC_R1B_ILLEGAL_CMD 0x0400 135 #define MMC_R1B_COM_CRC_ERR 0x0800 136 #define MMC_R1B_ERASE_SEQ_ERR 0x1000 137 #define MMC_R1B_ADDR_ERR 0x2000 138 #define MMC_R1B_PARAM_ERR 0x4000 139 140 #endif /* __REGS_MMC_H__ */ 141