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Searched refs:MIP_VSTIP (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dtime_helper.c58 if (timer_irq == MIP_VSTIP && in riscv_timer_write_timecmp()
72 if (timer_irq == MIP_VSTIP) { in riscv_timer_write_timecmp()
82 if (timer_irq == MIP_VSTIP) { in riscv_timer_write_timecmp()
160 if ((timer_irq == MIP_VSTIP) && in riscv_timer_disable_timecmp()
175 env->htimedelta, MIP_VSTIP); in riscv_timer_stce_changed()
177 riscv_timer_disable_timecmp(env, env->vstimer, MIP_VSTIP); in riscv_timer_stce_changed()
H A Dcpu_bits.h825 #define MIP_VSTIP (1 << IRQ_VS_TIMER) macro
851 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
H A Dcpu_helper.c431 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; in riscv_cpu_all_pending()
439 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); in riscv_cpu_mirq_pending()
737 vstip = env->vstime_irq ? MIP_VSTIP : 0; in riscv_cpu_interrupt()
751 mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; in riscv_cpu_update_mip()
H A Dcsr.c1686 env->htimedelta, MIP_VSTIP); in write_vstimecmp()
1696 env->htimedelta, MIP_VSTIP); in write_vstimecmph()
1831 static const uint64_t hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
3712 mask = mask & ~MIP_VSTIP; in rmw_mip64()
3725 old_mip |= env->vstime_irq ? MIP_VSTIP : 0; in rmw_mip64()
4993 env->htimedelta, MIP_VSTIP); in write_htimedelta()
5021 env->htimedelta, MIP_VSTIP); in write_htimedeltah()
/openbmc/qemu/hw/intc/
H A Driscv_aclint.c246 env->htimedelta, MIP_VSTIP); in riscv_aclint_mtimer_write()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c1298 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; in riscv_tcg_cpu_realize()