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Searched refs:MIP_VSTIP (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dtime_helper.c57 if (timer_irq == MIP_VSTIP) { in riscv_timer_write_timecmp()
67 if (timer_irq == MIP_VSTIP) { in riscv_timer_write_timecmp()
H A Dcpu_bits.h732 #define MIP_VSTIP (1 << IRQ_VS_TIMER) macro
758 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
H A Dcpu_helper.c464 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; in riscv_cpu_all_pending()
472 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); in riscv_cpu_mirq_pending()
481 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); in riscv_cpu_sirq_pending()
729 vstip = env->vstime_irq ? MIP_VSTIP : 0; in riscv_cpu_interrupt()
743 mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; in riscv_cpu_update_mip()
H A Dcsr.c1309 env->htimedelta, MIP_VSTIP); in write_vstimecmph()
1319 env->htimedelta, MIP_VSTIP); in read_stimecmp()
1454 static const uint64_t hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
2772 mask = mask & ~(MIP_STIP | MIP_VSTIP); in rmw_mip64()
2784 old_mip |= env->vstime_irq ? MIP_VSTIP : 0; in rmw_mip64()
3954 env->htimedelta, MIP_VSTIP);
3982 env->htimedelta, MIP_VSTIP);
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c1007 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; in riscv_tcg_cpu_realize()