Home
last modified time | relevance | path

Searched refs:MIP_STIP (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dtime_helper.c36 riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1)); in riscv_stimer_cb()
76 riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1)); in riscv_timer_write_timecmp()
153 if ((timer_irq == MIP_STIP) && !get_field(env->menvcfg, MENVCFG_STCE)) { in riscv_timer_disable_timecmp()
182 riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP); in riscv_timer_stce_changed()
184 riscv_timer_disable_timecmp(env, env->stimer, MIP_STIP); in riscv_timer_stce_changed()
H A Dcpu_bits.h824 #define MIP_STIP (1 << IRQ_S_TIMER) macro
836 #define SIP_STIP MIP_STIP
850 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
H A Dcsr.c1742 riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP); in write_stimecmp()
1758 riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP); in write_stimecmph()
1825 static const uint64_t mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP |
3711 mask = mask & ~MIP_STIP; in rmw_mip64()
3807 (env->mideleg | ~env->mvien)) | MIP_STIP; in rmw_mvip64()
3834 alias_mask &= ~MIP_STIP; in rmw_mvip64()
/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h54 #define MIP_STIP BIT(IRQ_S_TIMER) macro
62 #define SIP_STIP MIP_STIP
/openbmc/qemu/hw/intc/
H A Driscv_aclint.c244 riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP); in riscv_aclint_mtimer_write()