Home
last modified time | relevance | path

Searched refs:MIP_SEIP (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h724 #define MIP_SEIP (1 << IRQ_S_EXT) macro
733 #define SIP_SEIP MIP_SEIP
746 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
H A Dcsr.c1409 static const uint64_t mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP |
1411 static const uint64_t mvien_writable_mask = MIP_SSIP | MIP_SEIP |
2034 if (env->priv == PRV_S && env->mvien & MIP_SEIP && in rmw_xireg()
2106 if (env->mvien & MIP_SEIP && env->priv == PRV_S) { in rmw_xtopei()
2692 if (mask & MIP_SEIP) { in rmw_mip64()
2693 env->software_seip = new_val & MIP_SEIP; in rmw_mip64()
2694 new_val |= env->external_seip * MIP_SEIP; in rmw_mip64()
/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h57 #define MIP_SEIP BIT(IRQ_S_EXT) macro
/openbmc/qemu/hw/intc/
H A Driscv_imsic.c352 (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { in riscv_imsic_realize()
H A Dsifive_plic.c396 if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { in sifive_plic_realize()
H A Driscv_aplic.c881 (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { in riscv_aplic_realize()