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Searched refs:MIP_SEIP (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h828 #define MIP_SEIP (1 << IRQ_S_EXT) macro
837 #define SIP_SEIP MIP_SEIP
850 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h57 #define MIP_SEIP BIT(IRQ_S_EXT) macro
/openbmc/qemu/hw/intc/
H A Driscv_imsic.c354 (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { in riscv_imsic_realize()
H A Dsifive_plic.c403 if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { in sifive_plic_realize()