Searched refs:MIPSInst_RS (Results 1 – 3 of 3) sorted by relevance
107 regs->regs[MIPSInst_RS(ir)] | in mipsr6_emul()111 if (MIPSInst_RS(ir)) in mipsr6_emul()120 if (MIPSInst_RS(ir)) in mipsr6_emul()408 rs = regs->regs[MIPSInst_RS(ir)]; in mult_func()435 rs = regs->regs[MIPSInst_RS(ir)]; in multu_func()458 rs = regs->regs[MIPSInst_RS(ir)]; in div_func()480 rs = regs->regs[MIPSInst_RS(ir)]; in divu_func()506 rs = regs->regs[MIPSInst_RS(ir)]; in dmult_func()538 rs = regs->regs[MIPSInst_RS(ir)]; in dmultu_func()569 rs = regs->regs[MIPSInst_RS(ir)]; in ddiv_func()[all …]
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT) macro
1050 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()1068 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()1085 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()1102 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()1119 switch (MIPSInst_RS(ir)) { in cop1Emulate()1193 switch (MIPSInst_RS(ir)) { in cop1Emulate()1349 if (!(MIPSInst_RS(ir) & 0x10)) in cop1Emulate()1377 xcp->regs[MIPSInst_RS(ir)]; in cop1Emulate()