Home
last modified time | relevance | path

Searched refs:MII_BMCR_RESET (Results 1 – 11 of 11) sorted by relevance

/openbmc/qemu/include/hw/net/
H A Dmii.h46 #define MII_BMCR_RESET (1 << 15) macro
/openbmc/qemu/hw/net/fsl_etsec/
H A Dmiim.c81 etsec->phy_control = value & ~(MII_BMCR_RESET | MII_BMCR_FD); in miim_write_cycle()
/openbmc/qemu/hw/net/
H A Dmsf2-emac.c220 if (data & MII_BMCR_RESET) { in write_to_phy()
223 data &= ~MII_BMCR_RESET; in write_to_phy()
H A Dsunhme.c424 if (data & MII_BMCR_RESET) { in sunhme_mii_write()
426 data &= ~MII_BMCR_RESET; in sunhme_mii_write()
H A Dallwinner_emac.c106 if (value & MII_BMCR_RESET) { in RTL8201CP_mdio_write()
H A Dopencores_eth.c103 if (v & MII_BMCR_RESET) { in mii_write_bmcr()
H A Dnpcm_gmac.c675 data &= ~MII_BMCR_RESET; in npcm_gmac_mdio_access()
H A Dftgmac100.c386 if (val & MII_BMCR_RESET) { in do_phy_write()
H A De1000.c187 MII_BMCR_RESET | in set_phy_ctrl()
H A De1000e_core.c1764 MII_BMCR_RESET | in e1000e_set_phy_ctrl()
H A Digb_core.c2132 core->phy[MII_BMCR] = val & ~(0x3f | MII_BMCR_RESET | MII_BMCR_ANRESTART); in igb_set_phy_ctrl()