Home
last modified time | relevance | path

Searched refs:MIE (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/net/hamradio/
H A Dz8530.h110 #define MIE 8 /* Master Interrupt Enable */ macro
H A Dscc.c883 or(scc,R9,MIE); /* master interrupt enable */ in init_channel()
/openbmc/linux/drivers/tty/serial/
H A Dzs.h164 #define MIE 8 /* Master Interrupt Enable */ macro
H A Dsunzilog.h147 #define MIE 8 /* Master Interrupt Enable */ macro
H A Dip22zilog.h146 #define MIE 8 /* Master Interrupt Enable */ macro
H A Dpmac_zilog.h229 #define MIE 8 /* Master Interrupt Enable */ macro
H A Dsunzilog.c1356 up->curregs[R9] |= MIE; in sunzilog_init_hw()
1382 up->curregs[R9] |= MIE; in sunzilog_init_hw()
1591 up->curregs[R9] |= MIE; in sunzilog_init()
1628 up->curregs[R9] &= ~MIE; in sunzilog_exit()
H A Dip22zilog.c1142 up->curregs[R9] = NV | MIE; in ip22zilog_prepare()
H A Dzs.c116 MIE | DLC | NV, /* write 9 */
H A Dpmac_zilog.c836 uap->curregs[R9] |= NV | MIE; in __pmz_startup()
/openbmc/linux/drivers/i2c/busses/
H A Di2c-rcar.c58 #define MIE BIT(3) /* master if enable */ macro
92 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
93 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
94 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
/openbmc/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc291 D(0xeb23, CLT, RSY_b, MIE, r1_32u, m2_32u, 0, 0, ct, 0, 1)
292 D(0xeb2b, CLGT, RSY_b, MIE, r1_o, m2_64, 0, 0, ct, 0, 1)
778 C(0xec59, RISBGN, RIE_f, MIE, 0, r2, r1, 0, risbg, 0)