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Searched refs:MHPMEVENT_BIT_SINH (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h920 #define MHPMEVENT_BIT_SINH BIT_ULL(61) macro
930 MHPMEVENT_BIT_SINH | \
H A Dpmu.c160 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || in riscv_pmu_incr_ctr_rv64()
H A Dcsr.c959 inh_avail_mask |= riscv_has_ext(env, RVS) ? MHPMEVENT_BIT_SINH : 0; in write_mhpmevent()